*6800 type - Parallel Data(4-bit/8-bit), with Read/Write Line, Enable Line The Read/Write tells the module whether to write data or read data from the register. Some controllers may have more than one Enable Control Line. The Enable tells the LCD module that the data or instruction in the register is ready to be interpreted by the LCD Module. RS tells the LCD module if the information being sent is an Instruction or Data. The control lines used are Enable (E), Register Select (RS), and Read/Write (R/W). The parallel interface typically controls the LCD via 8 data pins and 3 control lines. Serial or Parallel Configuration to Microprocessor I think most devices need a pause before achieving synchornization.The most common LCD Module Interface Protocols are:ģ. From observation of devices that used RS-232 to receive data, I always remember seeing garbage if you hooked it up in the middle of a burst of data. I actually don't think anyone does that type of synchronization. If you pick up the channel in the middle of transmission you'll end up having to find the pattern of 10 repeating every 10 bits (8-bit data). So if the channel goes from idle to active, 0 will be the first thing you see. The RS-232 serial protocol has a start and stop bit, logic 0 and 1 respectively. EDIT: > it is nt simulating Why? Whats the problem? Draw a picture with different parallel input vectors and how the have to occur on the serial output. > 1st i got the data of 6 bit length > some other time when i get the data of length10 bit even in same way And HOW can cou see this difference of 4 bits on a 16 bit vector? How can you KNOW the witdh of the actual vector? > I think u got my point Yes, i do, but not vice versa. Thats exactly, what my previously posted code does. > Similarly some other time when i get the data of length10 bit even in > same way that should get serialized. > For example 1st i got the data of 6 bit length at > that time that data should be latched then it should get serialized. This means our logic should be 1 time programmed instead of runtime programmable. Similarly some other time when i get the data of length10 bit even in same way that should get serialized. Ya input is fixed length of 16 bit but this parallel to serial converter logic should be programmable when ever the data will arrive then dat should get serialized.įor example 1st i got the data of 6 bit length at that time that data should be latched then it should get serialized. ALL entity P2S is port ( Serial_out: out std_logic clk: in std_logic Parallel_data: in std_logic_vector( 15 downto 0) DataReady: in std_logic) end P2S architecture Behavioral of P2S is signal OldReady: std_logic:= '0' signal Shreg: std_logic_vector( 15 downto 0) begin process (clk) begin if (clk 'event and clk = '1') then Shreg.
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